Infineon /XMC4700 /SCU_GENERAL /MIRRSTS

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Interpret as MIRRSTS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)HDCLR 0 (value1)HDSET 0 (value1)HDCR 0 (value1)OSCSICTRL 0 (value1)OSCULCTRL 0 (value1)RTC_CTR 0 (value1)RTC_ATIM0 0 (value1)RTC_ATIM1 0 (value1)RTC_TIM0 0 (value1)RTC_TIM1 0 (value1)RMX 0 (value1)RTC_MSKSR 0 (value1)RTC_CLRSR

RMX=value1, HDCR=value1, HDCLR=value1, RTC_ATIM0=value1, RTC_TIM0=value1, OSCSICTRL=value1, HDSET=value1, RTC_CTR=value1, RTC_MSKSR=value1, RTC_ATIM1=value1, OSCULCTRL=value1, RTC_TIM1=value1, RTC_CLRSR=value1

Description

Mirror Write Status Register

Fields

HDCLR

HDCLR Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

HDSET

HDSET Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

HDCR

HDCR Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

OSCSICTRL

OSCSICTRL Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

OSCULCTRL

OSCULCTRL Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_CTR

RTC CTR Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_ATIM0

RTC ATIM0 Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_ATIM1

RTC ATIM1 Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_TIM0

RTC TIM0 Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_TIM1

RTC TIM1 Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RMX

Retention Memory Access Register Update Status

0 (value1): Ready

1 (value2): Busy

RTC_MSKSR

RTC MSKSSR Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

RTC_CLRSR

RTC CLRSR Mirror Register Write Status

0 (value1): Ready

1 (value2): Busy

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