Infineon /XMC4700 /SCU_HIBERNATE /HDCLR

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Interpret as HDCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)EPEV 0 (value1)ENEV 0 (value1)RTCEV 0 (value1)ULPWDG

ENEV=value1, RTCEV=value1, ULPWDG=value1, EPEV=value1

Description

Hibernate Domain Status Clear Register

Fields

EPEV

Wake-up Pin Event Positive Edge Clear

0 (value1): No effect

1 (value2): Clear wake-up event

ENEV

Wake-up Pin Event Negative Edge Clear

0 (value1): No effect

1 (value2): Clear wake-up event

RTCEV

RTC Event Clear

0 (value1): No effect

1 (value2): Clear wake-up event

ULPWDG

ULP WDG Alarm Clear

0 (value1): No effect

1 (value2): Clear watchdog alarm

Links

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