Infineon /XMC4700 /SCU_INTERRUPT /SRCLR

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Interpret as SRCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PRWARN 0 (value1)PI 0 (value1)AI 0 (value1)DLROVR 0 (value1)HDCLR 0 (value1)HDSET 0 (value1)HDCR 0 (value1)OSCSICTRL 0 (value1)OSCULCTRL 0 (value1)RTC_CTR 0 (value1)RTC_ATIM0 0 (value1)RTC_ATIM1 0 (value1)RTC_TIM0 0 (value1)RTC_TIM1 0 (value1)RMX

DLROVR=value1, OSCSICTRL=value1, HDCLR=value1, RTC_ATIM0=value1, PRWARN=value1, HDCR=value1, RTC_ATIM1=value1, OSCULCTRL=value1, RTC_CTR=value1, HDSET=value1, RTC_TIM1=value1, RTC_TIM0=value1, AI=value1, PI=value1, RMX=value1

Description

SCU Service Request Clear

Fields

PRWARN

WDT pre-warning Interrupt Clear

0 (value1): No effect

1 (value2): Clear the status bit

PI

RTC Periodic Interrupt Clear

0 (value1): No effect

1 (value2): Clear the status bit

AI

RTC Alarm Interrupt Clear

0 (value1): No effect

1 (value2): Clear the status bit

DLROVR

DLR Request Overrun Interrupt clear

0 (value1): No effect

1 (value2): Clear the status bit

HDCLR

HDCLR Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

HDSET

HDSET Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

HDCR

HDCR Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

OSCSICTRL

OSCSICTRL Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

OSCULCTRL

OSCULCTRL Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RTC_CTR

RTC CTR Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RTC_ATIM0

RTC ATIM0 Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RTC_ATIM1

RTC ATIM1 Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RTC_TIM0

RTC TIM0 Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RTC_TIM1

RTC TIM1 Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

RMX

Retention Memory Mirror Register Update Clear

0 (value1): No effect

1 (value2): Clear the status bit

Links

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