Infineon /XMC4700 /SCU_TRAP /TRAPCLR

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Interpret as TRAPCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SOSCWDGT 0 (value1)SVCOLCKT 0 (value1)UVCOLCKT 0 (value1)PET 0 (value1)BRWNT 0 (value1)ULPWDGT 0 (value1)BWERR0T 0 (value1)BWERR1T

BWERR0T=value1, ULPWDGT=value1, SVCOLCKT=value1, BRWNT=value1, BWERR1T=value1, UVCOLCKT=value1, SOSCWDGT=value1, PET=value1

Description

Trap Clear Register

Fields

SOSCWDGT

OSC_HP Oscillator Watchdog Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

SVCOLCKT

System VCO Lock Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

UVCOLCKT

USB VCO Lock Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

PET

Parity Error Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

BRWNT

Brown Out Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

ULPWDGT

OSC_ULP Oscillator Watchdog Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

BWERR0T

Peripheral Bridge 0 Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

BWERR1T

Peripheral Bridge 1 Trap Clear

0 (value1): No effect

1 (value2): Clear trap request

Links

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