Infineon /XMC4800 /DSD_CH0 /DICFG

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Interpret as DICFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)DSRC0 (value1)DSWC 0 (value1)ITRMODE 0 (value1)TSTRMODE 0TRSEL0 (value1)TRWC 0CSRC0 (value1)STROBE0 (value1)SCWC

DSWC=value1, STROBE=value1, DSRC=value1, ITRMODE=value1, TSTRMODE=value1, SCWC=value1, TRWC=value1

Description

Demodulator Input Configuration Register

Fields

DSRC

Input Data Source Select

0 (value1): Disconnected

2 (value2): External, from input A, direct

3 (value3): External, from input A, inverted

4 (value4): External, from input B, direct

5 (value5): External, from input B, inverted

DSWC

Write Control for Data Selection

0 (value1): No write access to data parameters

1 (value2): Bitfield DSRC can be written

ITRMODE

Integrator Trigger Mode

0 (value1): No integration trigger, integrator bypassed, INTEN = 0 all the time

1 (value2): Trigger event upon a falling edge

2 (value3): Trigger event upon a rising edge

3 (value4): No trigger, integrator active all the time, INTEN = 1 all the time

TSTRMODE

Timestamp Trigger Mode

0 (value1): No timestamp trigger

1 (value2): Trigger event upon a falling edge

2 (value3): Trigger event upon a rising edge

3 (value4): Trigger event upon each edge

TRSEL

Trigger Select

TRWC

Write Control for Trigger Parameters

0 (value1): No write access to trigger parameters

1 (value2): Bitfields TRSEL, TSTRMODE, ITRMODE can be written

CSRC

Sample Clock Source Select

1 (value2): External, from input A

2 (value3): External, from input B

3 (value4): External, from input C

4 (value5): External, from input D

15 (value6): Internal clock

STROBE

Data Strobe Generatoion Mode

0 (value1): No data strobe

1 (value2): Direct clock, a sample trigger is generated at each rising clock edge

2 (value3): Direct clock, a sample trigger is generated at each falling clock edge

3 (value4): Double data, a sample trigger is generated at each rising and falling clock edge

5 (value6): Double clock, a sample trigger is generated at every 2nd rising clock edge

6 (value7): Double clock, a sample trigger is generated at every 2nd falling clock edge

SCWC

Write Control for Strobe/Clock Selection

0 (value1): No write access to strobe/clock parameters

1 (value2): Bitfields STROBE, CSRC can be written

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