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Infineon /XMC4800 /SCU_CLK /ECATCLKCR

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Interpret as ECATCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ECADIV 0 (value1)ECATSEL

ECATSEL=value1

Description

EtherCAT Clock Control Register

Fields

ECADIV

EtherCAT Clock Divider Value
ECATSEL

EtherCAT Clock Selection Value

0 (value1): fPLLUSBclock

1 (value2): fPLLclock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data