Infineon /tle984x /ADC1 /CTRL3

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Interpret as CTRL3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MCM_DISABLED)MCM_PD_N 0 (SOFTWARE_MODE_DISABLE)SW_MODE 0 (ADC_EoC_FAIL_NOT_CLEAR)EoC_FAIL_CLR 0 (ADC_EoC_AVAILABLE)EoC_FAIL 0 (MCM_NOT_READY)MCM_RDY 0 (MICLK4)SAMPLE_TIME_HVCH 0 (MICLK4)SAMPLE_TIME_LVCH

EoC_FAIL_CLR=ADC_EoC_FAIL_NOT_CLEAR, SW_MODE=SOFTWARE_MODE_DISABLE, MCM_PD_N=MCM_DISABLED, MCM_RDY=MCM_NOT_READY, EoC_FAIL=ADC_EoC_AVAILABLE, SAMPLE_TIME_HVCH=MICLK4, SAMPLE_TIME_LVCH=MICLK4

Description

Measurement unit 1 control 3 register

Fields

MCM_PD_N

Power-down signal for MCM

0 (MCM_DISABLED): Measurement core module disabled

1 (MCM_ENABLED): Measurement core module enabled

SW_MODE

Software mode enable

0 (SOFTWARE_MODE_DISABLE): Sequencer running

1 (SOFTWARE_MODE_ENABLED): Sequencer stopped

EoC_FAIL_CLR

Fail of ADC end of conversion signal clear

0 (ADC_EoC_FAIL_NOT_CLEAR): No clear of EoC_FAIL flag

1 (ADC_EoC_FAIL_CLEAR): Clear of EoC_FAIL flag

EoC_FAIL

Fail of ADC end of conversion signal

0 (ADC_EoC_AVAILABLE): End of conversion signal was sent properly by ADC

1 (ADC_EoC_NOT_AVAILABLE): End of conversion signal was not sent properly by ADC

MCM_RDY

Ready signal for MCM (Measurement core module) after power on or reset

0 (MCM_NOT_READY): Measurement core module in start-up phase

1 (MCM_READY): Measurement core module start-up phase finished

SAMPLE_TIME_HVCH

Sample time of ADC1

0 (MICLK4): 4 ADC1_CLK clock periods

1 (MICLK6): 6 ADC1_CLK clock periods

2 (MICLK8): 8 ADC1_CLK clock periods

3 (MICLK10): 10 ADC1_CLK clock periods

4 (MICLK12): 12 ADC1_CLK clock periods (default)

5 (MICLK14): 14 ADC1_CLK clock periods

6 (MICLK16): 16 ADC1_CLK clock periods

7 (MICLK18): 18 ADC1_CLK clock periods

8 (MICLK20): 20 ADC1_CLK clock periods

9 (MICLK22): 22 ADC1_CLK clock periods

10 (MICLK4_1): 4 ADC1_CLK clock periods

11 (MICLK4_2): 4 ADC1_CLK clock periods

12 (MICLK4_3): 4 ADC1_CLK clock periods

13 (MICLK4_4): 4 ADC1_CLK clock periods

14 (MICLK4_5): 4 ADC1_CLK clock periods

15 (MICLK4_6): 4 ADC1_CLK clock periods

SAMPLE_TIME_LVCH

Sample time of ADC1

0 (MICLK4): 4 ADC1_CLK clock periods (default)

1 (MICLK6): 6 ADC1_CLK clock periods

2 (MICLK8): 8 ADC1_CLK clock periods

3 (MICLK10): 10 ADC1_CLK clock periods

4 (MICLK12): 12 ADC1_CLK clock periods

5 (MICLK14): 14 ADC1_CLK clock periods

6 (MICLK16): 16 ADC1_CLK clock periods

7 (MICLK18): 18 ADC1_CLK clock periods

8 (MICLK20): 20 ADC1_CLK clock periods

9 (MICLK22): 22 ADC1_CLK clock periods

10 (MICLK12_1): 12 ADC1_CLK clock periods

11 (MICLK12_2): 12 ADC1_CLK clock periods

12 (MICLK12_3): 12 ADC1_CLK clock periods

13 (MICLK12_4): 12 ADC1_CLK clock periods

14 (MICLK12_5): 12 ADC1_CLK clock periods

15 (MICLK12_6): 12 ADC1_CLK clock periods

Links

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