Infineon /tle984x /ADC1 /CTRL5

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Interpret as CTRL5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UNF)FILT_OUT_SEL_11_0

FILT_OUT_SEL_11_0=UNF

Description

Measurement unit 1 control 5 register

Fields

FILT_OUT_SEL_11_0

Output filter selection for channels 0 to 11

0 (UNF): ADC1 unfiltered data can be monitored in the corresponding FILT_OUTx registers

1 (CH0): Channel 0 IIR data enabled for FILT_OUT0 register

2 (CH1): Channel 1 IIR data enabled for FILT_OUT1 register

4 (CH2): Channel 2 IIR data enabled for FILT_OUT2 register

8 (CH3): Channel 3 IIR data enabled for FILT_OUT3 register

16 (CH4): Channel 4 IIR data enabled for FILT_OUT4 register

32 (CH5): Channel 5 IIR data enabled for FILT_OUT5 register

64 (CH6): Channel 6 IIR data enabled for FILT_OUT6 register

128 (CH7): Channel 7 IIR data enabled for FILT_OUT7 register

256 (CH8): Channel 8 IIR data enabled for FILT_OUT8 register

512 (CH9): Channel 9 IIR data enabled for FILT_OUT9 register

1024 (CH10): Channel 10 IIR data enabled for FILT_OUT10 register

2048 (CH11): Channel 11 IIR data enabled for FILT_OUT11 register

4095 (CH11_0): For channels 11-0 IIR data is enabled for FILT_OUTx registers

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