READY=NOT_READY, PD_N=POWER_DOWN, STRTUP_DIS=START_UP_ENABLE, SW_CH_SEL=CH0_EN, SOS=DISABLE, EOC=PENDING
ADC1 control and status register
PD_N | ADC1 Power-down signal 0 (POWER_DOWN): ADC1 is powered down 1 (ACTIVE): ADC1 is switched on |
SOS | ADC1 Start of sampling/conversion (software mode) 0 (DISABLE): No conversion is started 1 (ENABLE): Conversion is started |
READY | HVADC ready bit 0 (NOT_READY): Module in power-down or in init phase 1 (READY): Set automatically 5 ADC clock cycles after module is enabled |
CAL_SIGN | Output of comparator to steer gain/offset calibration |
EOC | ADC1 End of Conversion (software mode) 0 (PENDING): Conversion still running 1 (FINISHED): Conversion has finished |
SW_CH_SEL | Channel for software mode 0 (CH0_EN): Channel 0 enable 1 (CH1_EN): Channel 1 enable 2 (CH2_EN): Channel 2 enable 3 (CH3_EN): Channel 3 enable 4 (CH4_EN): Channel 4 enable 5 (CH5_EN): Channel 5 enable 6 (CH6_EN): Channel 6 enable 7 (CH7_EN): Channel 7 enable 8 (CH8_EN): Channel 8 enable 9 (CH9_EN): Channel 9 enable 10 (CH10_EN): Channel 10 enable 11 (CH11_EN): Channel 11 enable 12 (CH12_EN): Channel 12 enable |
STRTUP_DIS | DPP1 startup disable 0 (START_UP_ENABLE): DPP1 start-up enabled 1 (START_UP_DISABLE): DPP1 start-up disable |