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Infineon /tle984x /ADC1 /IRQEN_2

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Interpret as IRQEN_2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)VS_LO_IEN 0 (DISABLED)MON1_LO_IEN 0 (DISABLED)MON2_LO_IEN 0 (DISABLED)MON3_LO_IEN 0 (DISABLED)MON4_LO_IEN 0 (DISABLED)MON5_LO_IEN 0 (DISABLED)P2_1_LO_IEN 0 (DISABLED)P2_2_LO_IEN 0 (DISABLED)P2_3_LO_IEN 0 (DISABLED)P2_6_LO_IEN 0 (DISABLED)P2_7_LO_IEN 0 (DISABLED)VS_UP_IEN 0 (DISABLED)MON1_UP_IEN 0 (DISABLED)MON2_UP_IEN 0 (DISABLED)MON3_UP_IEN 0 (DISABLED)MON4_UP_IEN 0 (DISABLED)MON5_UP_IEN 0 (DISABLED)P2_1_UP_IEN 0 (DISABLED)P2_2_UP_IEN 0 (DISABLED)P2_3_UP_IEN 0 (DISABLED)P2_6_UP_IEN 0 (DISABLED)P2_7_UP_IEN

P2_7_UP_IEN=DISABLED, P2_3_LO_IEN=DISABLED, P2_3_UP_IEN=DISABLED, VS_UP_IEN=DISABLED, MON4_UP_IEN=DISABLED, MON5_LO_IEN=DISABLED, MON4_LO_IEN=DISABLED, P2_7_LO_IEN=DISABLED, P2_2_UP_IEN=DISABLED, P2_6_LO_IEN=DISABLED, VS_LO_IEN=DISABLED, P2_6_UP_IEN=DISABLED, MON1_UP_IEN=DISABLED, MON3_LO_IEN=DISABLED, P2_2_LO_IEN=DISABLED, P2_1_UP_IEN=DISABLED, MON2_LO_IEN=DISABLED, MON3_UP_IEN=DISABLED, P2_1_LO_IEN=DISABLED, MON5_UP_IEN=DISABLED, MON2_UP_IEN=DISABLED, MON1_LO_IEN=DISABLED

Description

ADC1 interrupt enable 2 register

Fields

VS_LO_IEN

ADC1 VS lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON1_LO_IEN

ADC1 MON 1 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON2_LO_IEN

ADC1 MON 2 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON3_LO_IEN

ADC1 MON 3 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON4_LO_IEN

ADC1 MON 4 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON5_LO_IEN

ADC1 MON 5 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_1_LO_IEN

ADC1 port 2.1 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_2_LO_IEN

ADC1 port 2.2 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_3_LO_IEN

ADC1 port 2.3 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_6_LO_IEN

ADC1 port 2.6 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_7_LO_IEN

ADC1 port 2.7 lower threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
VS_UP_IEN

ADC1 VS upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON1_UP_IEN

ADC1 MON 1 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON2_UP_IEN

ADC1 MON 2 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON3_UP_IEN

ADC1 MON 3 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON4_UP_IEN

ADC1 MON 4 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
MON5_UP_IEN

ADC1 MON 5 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_1_UP_IEN

ADC1 port 2.1 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_2_UP_IEN

ADC1 port 2.2 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_3_UP_IEN

ADC1 port 2.3 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_6_UP_IEN

ADC1 port 2.6 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled
P2_7_UP_IEN

ADC1 port 2.7 upper threshold interrupt enable

0 (DISABLED): Interrupt disabled

1 (ENABLED): Interrupt enabled

Links

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Register License

Copyright © 2022 Infineon Technologies AG Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and accompanying documentation covered by this license (the “Software”) to use, reproduce, display, distribute, execute, and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the Software is furnished to do so, all subject to the following: The copyright notices in the Software and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all derivative works of the Software, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor. THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data