Measurement unit 1 channel enable bits for cycle 0-1 register
SQ0 | Sequence 0 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable 128 (CH7_EN): Channel 7 enable 256 (CH8_EN): Channel 8 enable 512 (CH9_EN): Channel 9 enable 1024 (CH10_EN): Channel 10 enable 2048 (CH11_EN): Channel 11 enable |
SQ1 | Sequence 1 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable 128 (CH7_EN): Channel 7 enable 256 (CH8_EN): Channel 8 enable 512 (CH9_EN): Channel 9 enable 1024 (CH10_EN): Channel 10 enable 2048 (CH11_EN): Channel 11 enable |