Infineon /tle984x /ADC2 /CTRL4

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UNFILTERED)FILT_OUT_SEL_6_0

FILT_OUT_SEL_6_0=UNFILTERED

Description

Measurement unit control 4 register

Fields

FILT_OUT_SEL_6_0

Output filter selection for channels 0 to 6

0 (UNFILTERED): ADC2 unfiltered data can be monitored in the corresponding ADC2_FILT_OUTx registers

1 (CH_0): Channel 0 IIR data enabled for ADC2_FILT_OUT0 register

2 (CH_1): Channel 1 IIR data enabled for ADC2_FILT_OUT1 register

4 (CH_2): Channel 2 IIR data enabled for ADC2_FILT_OUT2 register

8 (CH_3): Channel 3 IIR data enabled for ADC2_FILT_OUT3 register

16 (CH_4): Channel 4 IIR data enabled for ADC2_FILT_OUT4 register

32 (CH_5): Channel 5 IIR data enabled for ADC2_FILT_OUT5 register

64 (CH_6): Channel 6 IIR data enabled for ADC2_FILT_OUT6 register

127 (ALL): For channels 6-0 IIR data is enabled for ADC2_FILT_OUTx registers

Links

() ()