Measurement channel enable bits for cycle 1-4 register
| SQ1 | Sequence 1 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable |
| SQ2 | Sequence 2 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable |
| SQ3 | Sequence 3 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable |
| SQ4 | Sequence 4 channel enable 1 (CH0_EN): Channel 0 enable 2 (CH1_EN): Channel 1 enable 4 (CH2_EN): Channel 2 enable 8 (CH3_EN): Channel 3 enable 16 (CH4_EN): Channel 4 enable 32 (CH5_EN): Channel 5 enable 64 (CH6_EN): Channel 6 enable |