Infineon /tle984x /ADC2 /SQ5_8

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Interpret as SQ5_8

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SQ50SQ60SQ7

Description

Measurement channel enable bits for cycle 5-8 register

Fields

SQ5

Sequence 5 channel enable

1 (CH0_EN): Channel 0 enable

2 (CH1_EN): Channel 1 enable

4 (CH2_EN): Channel 2 enable

8 (CH3_EN): Channel 3 enable

16 (CH4_EN): Channel 4 enable

32 (CH5_EN): Channel 5 enable

64 (CH6_EN): Channel 6 enable

SQ6

Sequence 6 channel enable

1 (CH0_EN): Channel 0 enable

2 (CH1_EN): Channel 1 enable

4 (CH2_EN): Channel 2 enable

8 (CH3_EN): Channel 3 enable

16 (CH4_EN): Channel 4 enable

32 (CH5_EN): Channel 5 enable

64 (CH6_EN): Channel 6 enable

SQ7

Sequence 7 channel enable

1 (CH0_EN): Channel 0 enable

2 (CH1_EN): Channel 1 enable

4 (CH2_EN): Channel 2 enable

8 (CH3_EN): Channel 3 enable

16 (CH4_EN): Channel 4 enable

32 (CH5_EN): Channel 5 enable

64 (CH6_EN): Channel 6 enable

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