Infineon /tle984x /CCU6 /ISR

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Interpret as ISR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (No_action)RCC60R 0 (No_action)RCC60F 0 (No_action)RCC61R 0 (No_action)RCC61F 0 (No_action)RCC62R 0 (No_action)RCC62F 0 (No_action)RT12OM 0 (No_action)RT12PM 0 (No_action)RT13CM 0 (No_action)RT13PM 0 (No_action)RTRPF 0 (No_action)RCHE 0 (No_action)RWHE 0 (No_action)RIDLE 0 (No_action)RSTR

RCC61R=No_action, RWHE=No_action, RCC62R=No_action, RCC62F=No_action, RT12OM=No_action, RCC60R=No_action, RTRPF=No_action, RCC60F=No_action, RSTR=No_action, RCHE=No_action, RT12PM=No_action, RIDLE=No_action, RCC61F=No_action, RT13CM=No_action, RT13PM=No_action

Description

Capture/compare interrupt status reset register

Fields

RCC60R

Reset capture, compare-match rising edge flag

0 (No_action): No action

1 (Reset): Bit CC60R in register IS will be reset

RCC60F

Reset capture, compare-match falling edge flag

0 (No_action): No action

1 (Reset): Bit CC60F in register IS will be reset

RCC61R

Reset capture, compare-match rising edge Flag

0 (No_action): No action

1 (Reset): Bit CC61R in register IS will be reset

RCC61F

Reset capture, compare-match falling edge flag

0 (No_action): No action

1 (Reset): Bit CC61F in register IS will be reset

RCC62R

Reset capture, compare-match rising edge flag

0 (No_action): No action

1 (Reset): Bit CC62R in register IS will be reset

RCC62F

Reset capture, compare-match falling edge flag

0 (No_action): No action

1 (Reset): Bit CC62F in register IS will be reset

RT12OM

Reset timer T12 one-match flag

0 (No_action): No action

1 (Reset): Bit T12OM in register IS will be reset

RT12PM

Reset timer T12 period-match flag

0 (No_action): No action

1 (Reset): Bit T12PM in register IS will be reset

RT13CM

Reset timer T13 compare-match flag

0 (No_action): No action

1 (Reset): Bit T13CM in register IS will be reset

RT13PM

Reset timer T13 period-Match flag

0 (No_action): No action

1 (Reset): Bit T13PM in register IS will be reset

RTRPF

Reset trap flag

0 (No_action): No action

1 (Reset): Bit TRPF in register IS will be reset (not taken into account while input CTRAP= 0 and TRPPEN = 1)

RCHE

Reset correct Hall event flag

0 (No_action): No action

1 (Reset): Bit CHE in register IS will be reset

RWHE

Reset wrong Hall event flag

0 (No_action): No action

1 (Reset): Bit WHE in register IS will be reset

RIDLE

Reset IDLE flag

0 (No_action): No action

1 (Reset): Bit IDLE in register IS will be reset

RSTR

Reset STR flag

0 (No_action): No action

1 (Reset): Bit STR in register IS will be reset

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