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Infineon /tle984x /CCU6 /ISS

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Interpret as ISS

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (No_action)SCC60R 0 (No_action)SCC60F 0 (No_action)SCC61R 0 (No_action)SCC61F 0 (No_action)SCC62R 0 (No_action)SCC62F 0 (No_action)ST12OM 0 (No_action)ST12PM 0 (No_action)ST13CM 0 (No_action)ST13PM 0 (No_action)STRPF 0 (No_action)SWHC 0 (No_action)SCHE 0 (No_action)SWHE 0 (No_action)SIDLE 0 (No_action)SSTR

SCC60R=No_action, ST12PM=No_action, SCC61R=No_action, SIDLE=No_action, SWHE=No_action, SWHC=No_action, ST13PM=No_action, SCC60F=No_action, ST13CM=No_action, SCC61F=No_action, ST12OM=No_action, SCC62F=No_action, SSTR=No_action, SCHE=No_action, STRPF=No_action, SCC62R=No_action

Description

Capture/compare interrupt status set register

Fields

SCC60R

Set capture, compare-match rising edge flag

0 (No_action): No action

1 (Set): Bit CC60R in register IS will be set
SCC60F

Set capture, compare-match falling edge flag

0 (No_action): No action

1 (Set): Bit CC60F in register IS will be set
SCC61R

Set capture, compare-match rising edge flag

0 (No_action): No action

1 (Set): Bit CC61R in register IS will be set
SCC61F

Set capture, compare-match falling edge flag

0 (No_action): No action

1 (Set): Bit CC61F in register IS will be set
SCC62R

Set capture, compare-match rising edge flag

0 (No_action): No action

1 (Set): Bit CC62R in register IS will be set
SCC62F

Set capture, compare-match falling edge flag

0 (No_action): No action

1 (Set): Bit CC62F in register IS will be set
ST12OM

Set timer T12 one-match flag

0 (No_action): No action

1 (Set): Bit T12OM in register IS will be set
ST12PM

Set timer T12 period-match flag

0 (No_action): No action

1 (Set): Bit T12PM in register IS will be set
ST13CM

Set timer T13 compare-match flag

0 (No_action): No action

1 (Set): Bit T13CM in register IS will be set
ST13PM

Set timer T13 period-match flag

0 (No_action): No action

1 (Set): Bit T13PM in register IS will be set
STRPF

Set trap flag

0 (No_action): No action

1 (Set): Bits TRPF and TRPS in register IS will be set
SWHC

Software Hall compare

0 (No_action): No action

1 (Set): The Hall compare action is triggered
SCHE

Set correct Hall event flag

0 (No_action): No action

1 (Set): Bit CHE in register IS will be set
SWHE

Set wrong Hall event flag

0 (No_action): No action

1 (Set): Bit WHE in register IS will be set
SIDLE

Set IDLE flag

0 (No_action): No action

1 (Set): Bit IDLE in register IS will be set
SSTR

Set STR flag

0 (No_action): No action

1 (Set): Bit STR in register IS will be set

Links

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Register License

Copyright © 2022 Infineon Technologies AG Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and accompanying documentation covered by this license (the “Software”) to use, reproduce, display, distribute, execute, and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the Software is furnished to do so, all subject to the following: The copyright notices in the Software and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all derivative works of the Software, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor. THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data