RegViz: Visualize T12MSEL Bitfield

Infineon /tle984x /CCU6 /T12MSEL

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Interpret as T12MSEL

HSYNC=Any, MSEL61=Compare_outputs_disabled, MSEL60=Compare_outputs_disabled, MSEL62=Compare_outputs_disabled, DBYP=Not_active

Description

T12 capture/compare mode select register

Fields

MSEL60	Capture/compare mode selection 0 (Compare_outputs_disabled): Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action 1 (Pin_CC6n_pin_COUT6n): Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action 2 (Pin_COUT6n_pin_CC6n): Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 3 (Pins_COUT6n_and_CC6n): Compare output on pins COUT6n and CC6n 4 (Double_register_Capture_modes): See Table “Register capture modes” 5 (Double_register_Capture_modes): See Table “Register capture modes” 6 (Double_register_Capture_modes): See Table “Register capture modes” 7 (Double_register_Capture_modes): See Table “Register capture modes” 8 (Hall_sensor_mode): See Table “Register capture modes”. In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 9 (Hysteresis_like_mode): See Table “Combined T12 modes” 10 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 11 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 12 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 13 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 14 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 15 (Multi_input_Capture_modes): See Table “Multi-input capture modes”
MSEL61	Capture/compare mode selection 0 (Compare_outputs_disabled): Compare outputs disabled, compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 1 (Pin_CC6n_pin_COUT6n): Compare output on pin CC6n, pin COUT6n can be used for I/O; no capture action 2 (Pin_COUT6n_pin_CC6n): Pin CC6n, compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 3 (Pins_COUT6n_and_CC6n): Compare output on pins COUT6n and CC6n 4 (Double_register_Capture_modes): See Table “Double-register capture modes” 5 (Double_register_Capture_modes): See Table “Double-register capture modes” 6 (Double_register_Capture_modes): See Table “Double-register capture modes” 7 (Double_register_Capture_modes): See Table “Double-register capture modes” 8 (Hall_sensor_mode): See Table “Combined T12 modes”. In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 9 (Hysteresis_like_mode): See Table “Combined T12 modes” 10 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 11 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 12 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 13 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 14 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 15 (Multi_input_Capture_modes): See Table “Multi-input capture modes”
MSEL62	Capture/compare mode selection 0 (Compare_outputs_disabled): Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action 1 (Pin_CC6n_pin_COUT6n): Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action 2 (Pin_COUT6n_pin_CC6n): Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 3 (Pins_COUT6n_and_CC6n): Compare output on pins COUT6n and CC6n 4 (Double_register_Capture_modes): See Table “Double-register capture modes” 5 (Double_register_Capture_modes): See Table “Double-register capture modes” 6 (Double_register_Capture_modes): See Table “Double-register capture modes” 7 (Double_register_Capture_modes): See Table “Double-register capture modes” 8 (Hall_sensor_mode): See Table “Combined T12 modes”. In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 9 (Hysteresis_like_mode): See Table “Combined T12 modes” 10 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 11 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 12 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 13 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 14 (Multi_input_Capture_modes): See Table “Multi-input capture modes” 15 (Multi_input_Capture_modes): See Table “Multi-input capture modes”
HSYNC	Hall synchronization 0 (Any): Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the sampling 1 (T13_compare_match): A T13 compare-match triggers the sampling 2 (T13_period_match): A T13 period-match triggers the sampling 3 (Hall): The Hall sampling triggered by hardware sources is switched off 4 (T12_period_match): A T12 period-match (while counting up) triggers the sampling 5 (T12_one_match): A T12 one-match (while counting down) triggers the sampling 6 (T12_compare_match_UP): A T12 compare-match of channel 0 (while counting up) triggers the sampling 7 (T12_compare_match_DOWN): A T12 compare-match of channel 0 (while counting down) triggers the sampling
DBYP	Delay bypass 0 (Not_active): The delay bypass is not active. The dead-time counter DTC0 is generating a delay after the source signal becomes active 1 (Active): The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern

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