STE13=DISABLED, CDIR=UP, T13CLK=1, T13PRE=DISABLED, CTM=Edge_aligned_mode, T12R=Stop, STE12=DISABLED, T13R=Stop, T12PRE=DISABLED, T12CLK=1
Timer control 0 register
| T12CLK | Timer T12 input clock select 0 (1): fT12 = fCCU 1 (2): fT12 = fCCU / 2 2 (4): fT12 = fCCU / 4 3 (8): fT12 = fCCU / 8 4 (16): fT12 = fCCU / 16 5 (32): fT12 = fCCU / 32 6 (64): fT12 = fCCU / 64 7 (128): fT12 = fCCU / 128 |
| T12PRE | Timer T12 prescaler bit 0 (DISABLED): The additional prescaler for T12 is disabled 1 (ENABLED): The additional prescaler for T12 is enabled |
| T12R | Timer T12 run bit 0 (Stop): Timer T12 is stopped 1 (Run): Timer T12 is running |
| STE12 | Timer T12 shadow transfer enable 0 (DISABLED): The shadow register transfer is disabled 1 (ENABLED): The shadow register transfer is enabled |
| CDIR | Count direction of timer T12 0 (UP): T12 counts up 1 (DOWN): T12 counts down |
| CTM | T12 operating mode 0 (Edge_aligned_mode): T12 always counts up and continues counting from zero after reaching the period value 1 (Center_aligned_mode): T12 counts down after detecting a period-match and counts up after detecting a one-match |
| T13CLK | Timer T13 input clock Select 0 (1): fT13 = fCCU 1 (2): fT13 = fCCU / 2 2 (4): fT13 = fCCU / 4 3 (8): fT13 = fCCU / 8 4 (16): fT13 = fCCU / 16 5 (32): fT13 = fCCU/ 32 6 (64): fT13 = fCCU / 64 7 (128): fT13 = fCCU / 128 |
| T13PRE | Timer T13 prescaler bit 0 (DISABLED): The additional prescaler for T13 is disabled 1 (ENABLED): The additional prescaler for T13 is enabled |
| T13R | Timer T13 run bit 0 (Stop): Timer T13 is stopped 1 (Run): Timer T13 is running |
| STE13 | Timer T13 shadow transfer enable 0 (DISABLED): The shadow register transfer is disabled 1 (ENABLED): The shadow register transfer is enabled |