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Infineon /tle984x /CPU /ICSR

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Interpret as ICSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (THREAD)VECTACTIVE0 (NOT_PENDING)VECTPENDING0 (NOT_PENDING)ISRPENDING 0 (NO_EFFECT)PENDSTCLR 0 (NOT_PENDING)PENDSTSET 0 (NO_EFFECT)PENDSVCLR 0 (NOT_PENDING)PENDSVSET 0 (NOT_PENDING)NMIPENDSET

PENDSTSET=NOT_PENDING, PENDSTCLR=NO_EFFECT, NMIPENDSET=NOT_PENDING, VECTPENDING=NOT_PENDING, PENDSVSET=NOT_PENDING, VECTACTIVE=THREAD, ISRPENDING=NOT_PENDING, PENDSVCLR=NO_EFFECT

Description

Interrupt control and state register

Fields

VECTACTIVE

VECTACTIVATE

0 (THREAD): Thread mode
VECTPENDING

VECTPENDING

0 (NOT_PENDING): No pending exceptions
ISRPENDING

Interrupt pending flag

0 (NOT_PENDING): Interrupt not pending

1 (PENDING): Interrupt is pending
PENDSTCLR

SysTick exception clear pending

0 (NO_EFFECT): No effect

1 (REMOVE): Removes the pending state from the SysTick exception
PENDSTSET

SysTick exception set pending

0 (NOT_PENDING): On writes, has no effect. On reads, SysTick exception is not pending

1 (PENDING): On writes, changes SysTick exception state to pending. On reads, SysTick exception is pending
PENDSVCLR

PendSV clear pending

0 (NO_EFFECT): No effect

1 (CLEAR): Remove pending state from the PENDSV exception
PENDSVSET

PendSV set pending

0 (NOT_PENDING): On writes, has no effect. On reads, PendSV exception is not pending

1 (PENDING): On writes, changes PendSV exception state to pending. On reads, PendSV is pending
NMIPENDSET

NMI set pending

0 (NOT_PENDING): On writes, has no effect. On reads, NMI exception is not pending

1 (PENDING): On writes, changes the NMI exception state to pending. On reads, NMI exception is pending

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data