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Infineon /tle984x /CPU /NVIC_ISER

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Interpret as NVIC_ISER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)Int_GPT1 0 (DISABLED)Int_GPT2 0 (DISABLED)Int_ADC2 0 (DISABLED)Int_ADC1 0 (DISABLED)Int_CCU6SR0 0 (DISABLED)Int_CCU6SR1 0 (DISABLED)Int_CCU6SR2 0 (DISABLED)Int_CCU6SR3 0 (DISABLED)Int_SSC1 0 (DISABLED)Int_SSC2 0 (DISABLED)Int_UART1 0 (DISABLED)Int_UART2 0 (DISABLED)Int_EXINT0 0 (DISABLED)Int_EXINT1 0 (DISABLED)Int_WAKEUP 0 (DISABLED)Int_LS1 0 (DISABLED)Int_LS2 0 (DISABLED)Int_HS1 0 (DISABLED)Int_HS2 0 (DISABLED)Int_DU 0 (DISABLED)Int_MON 0 (DISABLED)Int_PORT2

Int_LS2=DISABLED, Int_GPT1=DISABLED, Int_HS2=DISABLED, Int_SSC2=DISABLED, Int_PORT2=DISABLED, Int_SSC1=DISABLED, Int_CCU6SR0=DISABLED, Int_MON=DISABLED, Int_HS1=DISABLED, Int_ADC2=DISABLED, Int_UART2=DISABLED, Int_ADC1=DISABLED, Int_CCU6SR1=DISABLED, Int_CCU6SR2=DISABLED, Int_GPT2=DISABLED, Int_UART1=DISABLED, Int_LS1=DISABLED, Int_WAKEUP=DISABLED, Int_DU=DISABLED, Int_EXINT0=DISABLED, Int_CCU6SR3=DISABLED, Int_EXINT1=DISABLED

Description

Interrupt set-enable register

Fields

Int_GPT1

Interrupt set for GPT1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_GPT2

Interrupt set for GPT2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_ADC2

Interrupt set for MU, ADC2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_ADC1

Interrupt set for ADC1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_CCU6SR0

Interrupt set for CCU6 SR0

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_CCU6SR1

Interrupt set for CCU6 SR1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_CCU6SR2

Interrupt set for CCU6 SR2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_CCU6SR3

Interrupt set for CCU6 SR3

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_SSC1

Interrupt set for SSC1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_SSC2

Interrupt set for SSC2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_UART1

Interrupt set for UART1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_UART2

Interrupt set for UART2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_EXINT0

Interrupt set for external Int 0

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_EXINT1

Interrupt set for external Int 1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_WAKEUP

Interrupt set for WAKEUP

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_LS1

Interrupt set for LS1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_LS2

Interrupt set for LS2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_HS1

Interrupt set for HS1

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_HS2

Interrupt set for HS2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_DU

Interrupt set for differential unit

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_MON

Interrupt set for MON

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt
Int_PORT2

Interrupt set for PORT2

0 (DISABLED): No effect on write

1 (ENABLE): Enables the associated interrupt

Links

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Register License

Copyright © 2022 Infineon Technologies AG Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and accompanying documentation covered by this license (the “Software”) to use, reproduce, display, distribute, execute, and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the Software is furnished to do so, all subject to the following: The copyright notices in the Software and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all derivative works of the Software, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor. THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data