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Infineon /tle984x /CPU /SCR

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Interpret as SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NO_SLEEP)SLEEPONEXIT 0 (SLEEP)SLEEPDEEP 0 (SOME)SEVONPEND

SEVONPEND=SOME, SLEEPDEEP=SLEEP, SLEEPONEXIT=NO_SLEEP

Description

System control register

Fields

SLEEPONEXIT

Sleep on exit

0 (NO_SLEEP): Do not sleep when returning to Thread mode

1 (SLEEP): Enter sleep or deep sleep on return from an ISR to Thread mode
SLEEPDEEP

Sleep deep

0 (SLEEP): Sleep

1 (DEEP_SLEEP): Deep sleep
SEVONPEND

Send event on pending bit

0 (SOME): Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded

1 (ALL): Enabled events and all interrupts, including disabled interrupts, can wake up the processor

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data