Infineon /tle984x /CPU /SYSTICK_CSR

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Interpret as SYSTICK_CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)ENABLE 0 (DISABLE)TICKINT 0 (EXTCLK)CLKSOURCE 0 (COUNTFLAG)COUNTFLAG

CLKSOURCE=EXTCLK, ENABLE=DISABLE, TICKINT=DISABLE

Description

SysTick control and status register

Fields

ENABLE

Enable

0 (DISABLE): Counter disabled

1 (ENABLE): Counter enabled

TICKINT

TICKINT

0 (DISABLE): Counting down to 0 does not assert the SysTick exception request

1 (ENABLE): Counting down to 0 asserts the SysTick exception request

CLKSOURCE

CLK source

0 (EXTCLK): External reference clock (from fSYS/4)

1 (HCLK): Core clock (from fSYS)

COUNTFLAG

Count flag

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