Infineon /tle984x /GPT12E /T2CON

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Interpret as T2CON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0T2I0 (TIMER_MODE)T2M0 (STOP)T2R 0 (UP)T2UD 0 (T2UD)T2UDE 0 (T2R)T2RC 0 (ENABLED)T2IRIDIS 0 (NO_COUNT)T2EDGE 0 (NO_CHANGE)T2CHDIR 0 (UP)T2DIR

T2IRIDIS=ENABLED, T2UD=UP, T2R=STOP, T2RC=T2R, T2DIR=UP, T2CHDIR=NO_CHANGE, T2UDE=T2UD, T2M=TIMER_MODE, T2EDGE=NO_COUNT

Description

Timer T2 control register

Fields

T2I

Timer T2 input parameter selection

T2M

Timer T2 input mode control

0 (TIMER_MODE): Timer mode

1 (COUNTER_MODE): Counter mode

2 (GATED_LOW): Gated timer mode with gate active low

3 (GATED_HIGH): Gated timer mode with gate active high

4 (RELOAD_MODE): Reload mode

5 (CAPTURE_MODE): Capture mode

6 (INCREMENTAL_INTERFACE_MODE): Rotation detection mode

7 (INCREMENTAL_INTERFACE_MODE): Edge detection mode

T2R

Timer T2 input run bit

0 (STOP): Timer T2 stops

1 (RUN): Timer T2 runs

T2UD

Timer T2 up/down control

0 (UP): Timer T2 counts up

1 (DOWN): Timer T2 counts down

T2UDE

Timer T2 external up/down enable

0 (T2UD): Count direction is controlled by bit T2UD; input T2EUD is disconnected

1 (T2EUD): Count direction is controlled by input T2EUD

T2RC

Timer T2 remote control

0 (T2R): Timer T2 is controlled by its own run bit T2R

1 (T3R): Timer T2 is controlled by the run bit T3R of core timer T3, not by bit T2R

T2IRIDIS

Timer T2 interrupt disable

0 (ENABLED): Interrupt generation for T2CHDIR and T2EDGE interrupts in incremental interface mode is enabled

1 (DISABLED): Interrupt generation for T2CHDIR and T2EDGE interrupts in incremental interface mode is disabled

T2EDGE

Timer T2 edge detection

0 (NO_COUNT): No count edge was detected

1 (COUNT): A count edge was detected

T2CHDIR

Timer T2 count direction change

0 (NO_CHANGE): No change of count direction was detected

1 (CHANGE): A change of count direction was detected

T2DIR

Timer T2 rotation direction

0 (UP): Timer T2 counts up

1 (DOWN): Timer T2 counts down

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