T6OE=DISABLED, T6CLR=NOT_CLEARED, T6M=TIMER_MODE, T6SR=DISABLED, BPS2=4, T6UDE=T6UD, T6R=STOP, T6UD=UP
Timer T6 control register
| T6I | Timer T6 input parameter selection |
| T6M | Timer T6 mode control 0 (TIMER_MODE): Timer mode 1 (COUNTER_MODE): Counter mode 2 (GATED_LOW): Gated timer mode with gate active low 3 (GATED_HIGH): Gated timer mode with gate active high |
| T6R | Timer T6 input run bit 0 (STOP): Timer T3 stops 1 (RUN): Timer T3 runs |
| T6UD | Timer T6 up/down control 0 (UP): Timer T3 counts up 1 (DOWN): Timer T3 counts down |
| T6UDE | Timer T6 external up/down enable 0 (T6UD): Count direction is controlled by bit T6UD; input T6EUD is disconnected 1 (T6EUD): Count direction is controlled by input T6EUD |
| T6OE | Overflow/underflow output enable 0 (DISABLED): Alternate output function disabled 1 (T6OUT): State of T6 toggle latch is output on pin T6OUT |
| T6OTL | Timer T6 overflow toggle latch |
| BPS2 | GPT2 block prescaler control 0 (4): fGPT/4 1 (2): fGPT/2 2 (16): fGPT/16 3 (8): fGPT/8 |
| T6CLR | Timer T6 clear enable bit 0 (NOT_CLEARED): Timer T6 is not cleared on a capture event 1 (CLEARED): Timer T6 is cleared on a capture event |
| T6SR | Timer T6 reload mode enable 0 (DISABLED): Reload from register CAPREL disabled 1 (ENABLED): Reload from register CAPREL enabled |