Infineon /tle984x /PORT /P0_ALTSEL0

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Interpret as P0_ALTSEL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Const_0)PP0 0 (Const_0)PP1 0 (Const_0)PP2 0 (Const_0)PP3 0 (Const_0)PP4 0 (Const_0)PP5

PP5=Const_0, PP4=Const_0, PP2=Const_0, PP0=Const_0, PP1=Const_0, PP3=Const_0

Description

Port 0 alternate select 0 register

Fields

PP0

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

PP1

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

PP2

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

PP3

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

PP4

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

PP5

Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx)

0 (Const_0): Const_0

1 (Const_1): Const_1

Links

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