Infineon /tle984x /SCU /APCLK

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Interpret as APCLK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1)APCLK1FAC 0 (1)APCLK2FAC0 (LP_CLK)BGCLK_SEL 0 (2)BGCLK_DIV

BGCLK_DIV=2, BGCLK_SEL=LP_CLK, APCLK2FAC=1, APCLK1FAC=1

Description

Analog peripheral clock register

Fields

APCLK1FAC

Analog module clock factor

0 (1): Divide by 1

1 (2): Divide by 2

2 (3): Divide by 3

3 (4): Divide by 4

APCLK2FAC

Slow down clock divider for TFILT_CLK generation

0 (1): fSYS

1 (2): fSYS/2

2 (3): fSYS/3

3 (4): fSYS/4

4 (5): fSYS/5

5 (6): fSYS/6

6 (7): fSYS/7

7 (8): fSYS/8

8 (9): fSYS/9

9 (10): fSYS/10

10 (11): fSYS/11

11 (12): fSYS/12

30 (24): fSYS/24

31 (32): fSYS/32

BGCLK_SEL

Bandgap clock selection

0 (LP_CLK): LP_CLK is selected

1 (fSYS): fSYS is selected

BGCLK_DIV

Bandgap clock divider

0 (2): Divide by 2

1 (1): Divide by 1

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