Infineon /tle984x /SCU /APCLK_STS

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Interpret as APCLK_STS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RANGE)APCLK1STS 0 (RANGE)APCLK2STS 0 (NO_LOSS)APCLK3STS 0 (NOT_LOCKED)PLL_LOCK

APCLK1STS=RANGE, APCLK2STS=RANGE, APCLK3STS=NO_LOSS, PLL_LOCK=NOT_LOCKED

Description

Analog peripheral clock status register

Fields

APCLK1STS

Analog peripherals clock status

0 (RANGE): The MI_CLK clock is in the required range

1 (HIGHER): The MI_CLK clock exceeds the higher limit

2 (LOWER): The MI_CLK clock exceeds the lower limit

3 (OUTSIDE): The MI_CLK clock is not inside the specified limit

APCLK2STS

Analog peripherals clock status

0 (RANGE): The TFILT_CLK clock is in the required range

1 (HIGHER): The TFILT_CLK clock exceeds the higher limit

2 (LOWER): The TFILT_CLK clock exceeds the lower limit

3 (OUTSIDE): The TFILT_CLK clock is not inside the specified limit

APCLK3STS

Loss of clock status

0 (NO_LOSS): No loss of clock

1 (LOSS): Loss of lock occurred

PLL_LOCK

PLL LOCK status

0 (NOT_LOCKED): PLL has not locked

1 (LOCKED): PLL has locked

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