Infineon /tle984x /SCU /CMCON1

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Interpret as CMCON1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1)CLKREL0 (2)K2DIV 0 (2)K1DIV 0 (4)PDIV

K2DIV=2, PDIV=4, K1DIV=2, CLKREL=1

Description

Clock control 1 register

Fields

CLKREL

Slow down clock divider for fCCLK generation

0 (1): fSYS

1 (2): fSYS/2

2 (3): fSYS/3

3 (4): fSYS/4

4 (8): fSYS/8

5 (16): fSYS/16

6 (24): fSYS/24

7 (32): fSYS/32

8 (48): fSYS/48

9 (64): fSYS/64

10 (96): fSYS/96

11 (128): fSYS/128

12 (192): fSYS/192

13 (256): fSYS/256

14 (384): fSYS/384

15 (512): fSYS/512

K2DIV

PLL K2-divider

0 (2): K2 = 2

1 (3): K2 = 3

2 (4): K2 = 4

3 (5): K2 = 5

K1DIV

PLL K1-divider

0 (2): K1 = 2

1 (1): K1 = 1

PDIV

PLL PDIV-divider

0 (4): 4

1 (5): 5 (default)

2 (6_1): 6

3 (6_2): 6

Links

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