Infineon /tle984x /SCU /CMCON2

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Interpret as CMCON2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1)PBA0CLKREL

PBA0CLKREL=1

Description

Clock control 2 register

Fields

PBA0CLKREL

PBA0 clock divider

0 (1): Divide by 1

1 (2): Divide by 2

Links

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