OSCDISC=CONNECTED, LOCK=UNLOCKED, NDIV=48, RESLD=NO, VCOBYP=NORMAL
PLL control register
| LOCK | PLL lock status flag 0 (UNLOCKED): The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency 1 (LOCKED): The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation |
| RESLD | Restart lock detection 0 (NO): No effect 1 (RESET): Reset lock flag and restart lock detection |
| OSCDISC | Oscillator disconnect 0 (CONNECTED): Oscillator is connected to the PLL 1 (DISCONNECTED): Oscillator is disconnected to the PLL |
| VCOBYP | PLL VCO bypass mode select 0 (NORMAL): Normal (or free running) operation (default) 1 (PRESCALER): Prescaler mode; VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider) |
| NDIV | PLL N-divider 0 (48): N = 48 1 (50): N = 50 2 (51): N = 51 3 (52): N = 52 4 (54): N = 54 5 (60): N = 60 6 (67): N = 67 7 (72): N = 72 8 (75): N = 75 9 (78): N = 78 10 (80): N = 80 11 (88): N = 88 12 (90): N = 90 13 (94): N =94 14 (100): N = 100 15 (160): N = 160 |
| UNPROT_OSCDISC | Unprotect write access of OSC_DISC |
| UNPROT_VCOBYP | Unprotect write access of VCO_BYP |