Infineon /tle984x /SCU /SYSCON0

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Interpret as SYSCON0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1)NVMCLKFAC 0 (PLL)SYSCLKSEL

SYSCLKSEL=PLL, NVMCLKFAC=1

Description

System control 0 register

Fields

NVMCLKFAC

NVM access clock factor

0 (1): Divide by 1

1 (2): Divide by 2

2 (3): Divide by 3

3 (4): Divide by 4

SYSCLKSEL

System clock select

0 (PLL): The PLL clock output signal fPLL is used

1 (OSC): The direct clock input from fOSC is used

2 (LP_CLK): The direct low-precision clock input from fLP_CLK is used

3 (INTOSC): The direct input from internal oscillator fINTOSC is used

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