Keil /AT32A403Axx_v2 /DMA1 /C5CTRL

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Interpret as C5CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHEN)CHEN 0 (FDTIEN)FDTIEN 0 (HDTIEN)HDTIEN 0 (DTERRIEN)DTERRIEN 0 (DTD)DTD 0 (LM)LM 0 (PINCM)PINCM 0 (MINCM)MINCM 0PWIDTH 0MWIDTH 0CHPL 0 (M2M)M2M

Description

DMA channel configuration register

Fields

CHEN

Channel enable

FDTIEN

Full data transfer interrupt enable

HDTIEN

Half data transfer interrupt enable

DTERRIEN

Data transfer error interrupt enable

DTD

Data transfer direction

LM

Loop mode

PINCM

Peripheral address increment mode

MINCM

Memory address increment mode

PWIDTH

Peripheral data bit width

MWIDTH

Memory data bit width

CHPL

Channel Priority level

M2M

Memory to memory mode

Links

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