Keil /AT32F402xx_v2 /CRM /APB1LPEN

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Interpret as APB1LPEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TMR2LPEN)TMR2LPEN 0 (TMR3LPEN)TMR3LPEN 0 (TMR4LPEN)TMR4LPEN 0 (TMR6LPEN)TMR6LPEN 0 (TMR7LPEN)TMR7LPEN 0 (TMR13LPEN)TMR13LPEN 0 (TMR14LPEN)TMR14LPEN 0 (WWDTLPEN)WWDTLPEN 0 (SPI2LPEN)SPI2LPEN 0 (SPI3LPEN)SPI3LPEN 0 (USART2LPEN)USART2LPEN 0 (USART3LPEN)USART3LPEN 0 (USART4LPEN)USART4LPEN 0 (USART5LPEN)USART5LPEN 0 (I2C1CPEN)I2C1CPEN 0 (I2C2CPEN)I2C2CPEN 0 (I2C3CPEN)I2C3CPEN 0 (CAN1LPEN)CAN1LPEN 0 (PWCLPEN)PWCLPEN 0 (UART7LPEN)UART7LPEN 0 (UART8LPEN)UART8LPEN

Description

APB1 peripheral Low-power clock enable register (CRM_APB1LPEN)

Fields

TMR2LPEN

Timer2 clock enable during sleep mode

TMR3LPEN

Timer3 clock enable during sleep mode

TMR4LPEN

Timer4 clock enable during sleep mode

TMR6LPEN

Timer6 clock enable during sleep mode

TMR7LPEN

Timer7 clock enable during sleep mode

TMR13LPEN

Timer13 clock enable during sleep mode

TMR14LPEN

Timer14 clock enable during sleep mode

WWDTLPEN

WWDT clock enable during sleep mode

SPI2LPEN

SPI2 clock enable during sleep mode

SPI3LPEN

SPI3 clock enable during sleep mode

USART2LPEN

USART2 clock enable during sleep mode

USART3LPEN

USART3 clock enable during sleep mode

USART4LPEN

USART4 clock enable during sleep mode

USART5LPEN

USART5 clock enable during sleep mode

I2C1CPEN

I2C1 clock enable during sleep mode

I2C2CPEN

I2C2 clock enable during sleep mode

I2C3CPEN

I2C3 clock enable during sleep mode

CAN1LPEN

CAN1 clock enable during sleep mode

PWCLPEN

PWC clock enable during sleep mode

UART7LPEN

UART7 clock enable during sleep mode

UART8LPEN

UART8 clock enable during sleep mode

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