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Keil /AT32F402xx_v2 /SPI1 /CTRL1

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Interpret as CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLKPHA)CLKPHA 0 (CLKPOL)CLKPOL 0 (MSTEN)MSTEN 0MDIV2_0 0 (SPIEN)SPIEN 0 (LTF)LTF 0 (SWCSIL)SWCSIL 0 (SWCSEN)SWCSEN 0 (ORA)ORA 0 (FBN)FBN 0 (NTC)NTC 0 (CCEN)CCEN 0 (SLBTD)SLBTD 0 (SLBEN)SLBEN

Description

control register 1

Fields

CLKPHA

Clock phase
CLKPOL

Clock polarity
MSTEN

Master enable
MDIV2_0

Master clock frequency division bit2-0
SPIEN

SPI enable
LTF

LSB transmit first
SWCSIL

Software CS internal level
SWCSEN

Software CS enable
ORA

Only receive active
FBN

frame bit num
NTC

Next transmission CRC
CCEN

CRC calculation enable
SLBTD

Single line bidirectional half-duplex transmission direction
SLBEN

Single line bidirectional half-duplex enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data