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Keil /AT32F402xx_v2 /SPI1 /I2SCLK

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Interpret as I2SCLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2SDIV7_00 (I2SODD)I2SODD 0 (I2SMCLKOE)I2SMCLKOE 0I2SDIV9_8

Description

I2S clock register

Fields

I2SDIV7_0

I2S division bit7 to bit0
I2SODD

Odd result for I2S division
I2SMCLKOE

I2S master clock output enable
I2SDIV9_8

I2S division bit9 and bit8

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data