Clock configuration register (CRM_CFG)
| SCLKSEL | System clock select |
| SCLKSTS | System Clock select Status |
| AHBDIV | AHB division |
| APB1DIV | APB1 division |
| APB2DIV | APB2 division |
| ADCDIV1_0 | ADC division bit1 and bit0 |
| PLLRCS | PLL reference clock select |
| PLLHEXTDIV | HEXT division selection for PLL entry clock |
| PLLMULT3_0 | PLL Multiplication Factor bit3 to bit0 |
| USBDIV1_0 | USB division bit1 and bit0 |
| CLKOUT_SEL | Clock output selection bit2 to bit0 |
| USBDIV2 | USB division bit2 |
| ADCDIV2 | ADC division bit2 |
| PLLMULT5_4 | PLL Multiplication Factor bit5 and bit4 |
| PLLRANGE | PLL clock output frequency up 72MHz or not |