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Keil /AT32F403xx_v2 /DMA2 /CLR

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Interpret as CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GFC1)GFC1 0 (FDTFC1)FDTFC1 0 (HDTFC1)HDTFC1 0 (DTERRFC1)DTERRFC1 0 (GFC2)GFC2 0 (FDTFC2)FDTFC2 0 (HDTFC2)HDTFC2 0 (DTERRFC2)DTERRFC2 0 (GFC3)GFC3 0 (FDTFC3)FDTFC3 0 (HDTFC3)HDTFC3 0 (DTERRFC3)DTERRFC3 0 (GFC4)GFC4 0 (FDTFC4)FDTFC4 0 (HDTFC4)HDTFC4 0 (DTERRFC4)DTERRFC4 0 (GFC5)GFC5 0 (FDTFC5)FDTFC5 0 (HDTFC5)HDTFC5 0 (DTERRFC5)DTERRFC5

Description

DMA interrupt flag clear register (DMA_CLR)

Fields

GFC1

Channel 1 Global flag clear
FDTFC1

Channel 1 full data transfer flag clear
HDTFC1

Channel 1 half data transfer flag clear
DTERRFC1

Channel 1 data transfer error flag clear
GFC2

Channel 2 Global flag clear
FDTFC2

Channel 2 full data transfer flag clear
HDTFC2

Channel 2 half data transfer flag clear
DTERRFC2

Channel 2 data transfer error flag clear
GFC3

Channel 3 Global flag clear
FDTFC3

Channel 3 full data transfer flag clear
HDTFC3

Channel 3 half data transfer flag clear
DTERRFC3

Channel 3 data transfer error flag clear
GFC4

Channel 4 Global flag clear
FDTFC4

Channel 4 full data transfer flag clear
HDTFC4

Channel 4 half data transfer flag clear
DTERRFC4

Channel 4 data transfer error flag clear
GFC5

Channel 5 Global flag clear
FDTFC5

Channel 5 full data transfer flag clear
HDTFC5

Channel 5 half data transfer flag clear
DTERRFC5

Channel 5 data transfer error flag clear

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data