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Keil /AT32F407xx_v2 /SPI1 /CTRL2

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Interpret as CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMAREN)DMAREN 0 (DMATEN)DMATEN 0 (HWCSOE)HWCSOE 0 (ERRIE)ERRIE 0 (RDBFIE)RDBFIE 0 (TDBEIE)TDBEIE 0 (MDIV3)MDIV3

Description

control register 2

Fields

DMAREN

DMA receive enable
DMATEN

DMA transmit enable
HWCSOE

Hardware CS output enable
ERRIE

Error interrupt enable
RDBFIE

Receive data buffer full interrupt enable
TDBEIE

Transmit data buffer empty interrupt enable
MDIV3

Master clock frequency division bit3

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data