Keil /AT32F413xx_v2 /DMA1 /C5CTRL

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Interpret as C5CTRL

31282724232019161512118743000000000000000000000000000000000000000000 (CHEN)CHEN0 (FDTIEN)FDTIEN0 (HDTIEN)HDTIEN0 (DTERRIEN)DTERRIEN0 (DTD)DTD0 (LM)LM0 (PINCM)PINCM0 (MINCM)MINCM0PWIDTH0MWIDTH0CHPL0 (M2M)M2M

Description

DMA channel configuration register

Fields

CHEN

Channel enable

FDTIEN

Full data transfer interrupt enable

HDTIEN

Half data transfer interrupt enable

DTERRIEN

Data transfer error interrupt enable

DTD

Data transfer direction

LM

Loop mode

PINCM

Peripheral address increment mode

MINCM

Memory address increment mode

PWIDTH

Peripheral data bit width

MWIDTH

Memory data bit width

CHPL

Channel Priority level

M2M

Memory to memory mode

Links

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