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Keil /AT32F415xx_v2 /ACC /CTRL1

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Interpret as CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CALON)CALON 0 (ENTRIM)ENTRIM 0 (EIEN)EIEN 0 (CALRDYIEN)CALRDYIEN 0STEP

Description

Control register 1

Fields

CALON

Internal high-speed clock calibration ready
ENTRIM

Enable trim
EIEN

RSLOST error interrupt enable
CALRDYIEN

CALRDY interrupt enable
STEP

STEP

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data