Keil /AT32F415xx_v2 /SDIO1 /CLKCTRL

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Interpret as CLKCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKPSC0 (CLKEN)CLKEN 0 (PWRSVG)PWRSVG 0 (BYPS)BYPS 0BUSWIDTH 0 (CLKEDG)CLKEDG 0 (FLWCTRLEN)FLWCTRLEN 0CLKPSC98

Description

SDI clock control register (SDIO_CLKCTRL)

Fields

CLKPSC

Clock divide factor

CLKEN

Clock enable bit

PWRSVG

Power saving configuration bit

BYPS

Clock divider bypass enable bit

BUSWIDTH

Wide bus mode enable bit

CLKEDG

SDIO_CK dephasing selection bit

FLWCTRLEN

HW Flow Control enable

CLKPSC98

Clock divide factor bit9 and bit8

Links

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