Keil /AT32F435xx_v2 /CRM /AHBLPEN1

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Interpret as AHBLPEN1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIOALPEN)GPIOALPEN 0 (GPIOBLPEN)GPIOBLPEN 0 (GPIOCLPEN)GPIOCLPEN 0 (GPIODLPEN)GPIODLPEN 0 (GPIOELPEN)GPIOELPEN 0 (GPIOFLPEN)GPIOFLPEN 0 (GPIOGLPEN)GPIOGLPEN 0 (GPIOHLPEN)GPIOHLPEN 0 (CRCLPEN)CRCLPEN 0 (FLASHLPEN)FLASHLPEN 0 (SRAM1LPEN)SRAM1LPEN 0 (SRAM2LPEN)SRAM2LPEN 0 (EDMALPEN)EDMALPEN 0 (DMA1LPEN)DMA1LPEN 0 (DMA2LPEN)DMA2LPEN 0 (EMACLPEN)EMACLPEN 0 (EMACTXLPEN)EMACTXLPEN 0 (EMACRXLPEN)EMACRXLPEN 0 (EMACPTPLPEN)EMACPTPLPEN 0 (OTGFS2LPEN)OTGFS2LPEN

Description

AHB Low-power Peripheral Clock enable register 1 (CRM_AHBLPEN1)

Fields

GPIOALPEN

IO A clock enable during sleep mode

GPIOBLPEN

IO B clock enable during sleep mode

GPIOCLPEN

IO C clock enable during sleep mode

GPIODLPEN

IO D clock enable during sleep mode

GPIOELPEN

IO E clock enable during sleep mode

GPIOFLPEN

IO F clock enable during sleep mode

GPIOGLPEN

IO G clock enable during sleep mode

GPIOHLPEN

IO H clock enable during sleep mode

CRCLPEN

CRC clock enable during sleep mode

FLASHLPEN

Flash clock enable during sleep mode

SRAM1LPEN

SRAM1 clock enable during sleep mode

SRAM2LPEN

SRAM2 clock enable during sleep mode

EDMALPEN

EDMA clock enable during sleep mode

DMA1LPEN

DMA1 clock enable during sleep mode

DMA2LPEN

DMA2 clock enable during sleep mode

EMACLPEN

EMAC clock enable during sleep mode

EMACTXLPEN

EMAC Tx clock enable during sleep mode

EMACRXLPEN

EMAC Rx clock enable during sleep mode

EMACPTPLPEN

EMAC PTP clock enable during sleep mode

OTGFS2LPEN

OTGFS2 clock enable during sleep mode

Links

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