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Keil /AT32F435xx_v2 /CRM /AHBLPEN2

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Interpret as AHBLPEN2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DVPLPEN)DVPLPEN 0 (OTGFS1LPEN)OTGFS1LPEN 0 (SDIO1LPEN)SDIO1LPEN

Description

AHB peripheral Low-power clock enable register 2 (CRM_AHBLPEN2)

Fields

DVPLPEN

DVP clock enable during sleep mode
OTGFS1LPEN

OTGFS1 clock enable during sleep mode
SDIO1LPEN

SDIO1 clock enable during sleep mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data