Keil /AT32F435xx_v2 /CRM /APB2LPEN

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Interpret as APB2LPEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TMR1LPEN)TMR1LPEN 0 (TMR8LPEN)TMR8LPEN 0 (USART1LPEN)USART1LPEN 0 (USART6LPEN)USART6LPEN 0 (ADC1CPEN)ADC1CPEN 0 (ADC2CPEN)ADC2CPEN 0 (ADC3EN)ADC3EN 0 (SPI1LPEN)SPI1LPEN 0 (SPI4LPEN)SPI4LPEN 0 (SCFGLPEN)SCFGLPEN 0 (TMR9LPEN)TMR9LPEN 0 (TMR10LPEN)TMR10LPEN 0 (TMR11LPEN)TMR11LPEN 0 (TMR20LPEN)TMR20LPEN 0 (ACCLPEN)ACCLPEN

Description

APB2 peripheral Low-power clock enable register (CRM_APB2LPEN)

Fields

TMR1LPEN

Timer1 clock enable during sleep mode

TMR8LPEN

Timer8 clock enable during sleep mode

USART1LPEN

USART1 clock enable during sleep mode

USART6LPEN

USART6 clock enable during sleep mode

ADC1CPEN

ADC1 clock enable during sleep mode

ADC2CPEN

ADC2 clock enable during sleep mode

ADC3EN

ADC3 clock enable during sleep mode

SPI1LPEN

SPI1 clock enable during sleep mode

SPI4LPEN

SPI4 clock enable during sleep mode

SCFGLPEN

SCFG clock enable during sleep mode

TMR9LPEN

Timer9 clock enable during sleep mode

TMR10LPEN

Timer10 clock enable during sleep mode

TMR11LPEN

Timer11 clock enable during sleep mode

TMR20LPEN

Timer20 clock enable during sleep mode

ACCLPEN

ACC clock enable during sleep mode

Links

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