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Keil /AT32F435xx_v2 /CRM /PLLCFG

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Interpret as PLLCFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_MS0PLL_NS0PLL_FR 0 (PLLRCS)PLLRCS

Description

PLL configuration register (CRM_PLLCFG)

Fields

PLL_MS

PLL pre-division
PLL_NS

PLL frequency multiplication factor
PLL_FR

PLL post-division
PLLRCS

PLL reference clock select

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data