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Keil /AT32F435xx_v2 /DAC /DDTH12L

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Interpret as DDTH12L

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DD1DT12L0DD2DT12L

Description

DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved

Fields

DD1DT12L

DAC1 12-bit left-aligned data
DD2DT12L

DAC2 12-bit right-aligned data

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data