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Keil /AT32F435xx_v2 /DAC /DDTH12R

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Interpret as DDTH12R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DD1DT12R0DD2DT12R

Description

Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved

Fields

DD1DT12R

DAC1 12-bit right-aligned data
DD2DT12R

DAC2 12-bit right-aligned data

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data