CCD=non_div, SYSCLK_RDY=busy, SYSCLK_DIV=div1, SYSCLK_SEL=IPO
Clock Control.
| SYSCLK_DIV | Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 0 (div1): Divide by 1. 1 (div2): Divide by 2. 2 (div4): Divide by 4. 3 (div8): Divide by 8. 4 (div16): Divide by 16. 5 (div32): Divide by 32. 6 (div64): Divide by 64. 7 (div128): Divide by 128. |
| SYSCLK_SEL | Clock Source Select. This 3 bit field selects the source for the system clock. 0 (IPO): Internal Primary Oscilatior Clock 3 (INRO): 8kHz Internal Nano Ring Oscillator is used for the system clock. 5 (IBRO): The internal Baud Rate oscillator is used for the system clock. |
| SYSCLK_RDY | Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 0 (busy): Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 1 (ready): System clock running from CLKSEL clock source. |
| CCD | Cryptographic clock divider 0 (non_div): The cryptographic accelerator clock is running in non-divided mode. 1 (div): The cryptographic accelerator clock is running in divided mode. |
| IPO_EN | 96MHz High Frequency Internal Reference Clock Enable. |
| IBRO_EN | 8MHz High Frequency Internal Reference Clock Enable. |
| IBRO_VS | 7.3728MHz Internal Oscillator Voltage Source Select |
| IPO_RDY | Internal Primary Oscillator Ready. |
| IBRO_RDY | Internal Baud Rate Oscillator Ready. |
| INRO_RDY | Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. |