Maxim-Integrated /max32520 /GCR /PCLKDIS1

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Interpret as PCLKDIS1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRNG)TRNG 0 (WDT0)WDT0 0 (WDT1)WDT1 0 (SFES)SFES

Description

Peripheral Clock Disable.

Fields

TRNG

TRNG Disable.

WDT0

WDT0 Clock Disable

WDT1

WDT1 Clock Disable

SFES

Serial Flash emulation slave Clock Disable

Links

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