PCFWEN=blocked, AON_CLKDIV=div_4
Peripheral Clock Divider.
| PCF | These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. 2 (96MHz): undefined 3 (48MHz): undefined 4 (24MHz): undefined 5 (12MHz): undefined 6 (6MHz): undefined 7 (3MHz): undefined |
| PCFWEN | PCF Write Enable. This bit allows the PCF Register bits to be updated by Software. 0 (blocked): Writes to PCF are blocked. 1 (allowed): Writes to PCF are allowed |
| AON_CLKDIV | Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. 0 (div_4): PCLK divide by 4. 1 (div_8): PCLK divide by 8. 2 (div_16): PCLK divide by 16. 3 (div_32): PCLK divide by 32. |